The invention relates in general to a bus system and in particular to a bus system having a reduced number of control lines.
To transmit data between two devices, bus systems are conventionally employed with a bus having bus interfaces that connect the devices transmitting and receiving the data. In most bus systems, it is predetermined as to which of the connected devices is the controlling bus device (master) and which is the serving bus device (slave). Frequent use is also made of a direct memory access (DMA) device.
In computers, buses are typically employed to transmit data between the different devices, where control of the data bus is handled by a central processing unit (CPU). For purposes of control, the CPU has, in addition to the data bus for data transmission, an address bus to transmit the address of the device to which or from which data is to be transmitted through the data bus. There are also control lines as part of a control bus leading from the CPU to the individual devices to signal whether a device is to receive data through the data bus or send data through the data bus. In addition, the control lines determine the time of transmission through the data bus. The process thus involves a central control of the data transmission through the data bus where the central control device (i.e., CPU) enables the data bus for the individual connected devices.
A generally known approach is the principle of handshaking through which the individual devices connected to a data bus communicate with each other, where a CPU also organizes coordination of the data access. In addition to the data bus to transmit data between the individual devices, there are typically at least three control lines. Usually, strobe-acknowledge or interrupt signals are transmitted on the control lines. Data input to the CPU is performed through the data bus when a connected peripheral device applies the data to be transmitted to the data bus and uses a strobe or interrupt signal to signal the CPU that data are available for transmission. The interrupt signal signals the peripheral device whether an input buffer of the receiving device is empty and therefore additional data can be applied to the data bus. As soon as the process has initiated the retrieval of data from the input buffer, the interrupt signal is canceled, thereby signaling to the connected peripheral device that another data transmission can be implemented.
In the case of a data output from the CPU to the peripheral device, the CPU applies the data to the control lines of the data bus and triggers a write pulse. The peripheral device acknowledges retrieval or receipt of the data with the acknowledge signal, after which a reset of the interrupt signal notifies the CPU that the data bus is ready for a new transmission. In this arrangement as well, assignment of the data bus to transmit data to the individual connected devices is thus performed by the CPU.
Generally known software and hardware interrupts are used to process the interrupts. Hardware interrupts are directed to interrupt control lines which also enable prioritization of various parallel-received inquiries for data bus arbitration. Conventional bus systems thus have a data bus, an address bus, and a control bus or corresponding signaling lines and control lines.
Currently available processor chips for digital signal processing, or their central control devices, are usually designed with a large number of random access memory locations (RAM) on the chip or die. Thus, these chips are usually fabricated using the relatively newest and expensive technology. For many reasons, it is not practical to integrate a multiplicity of interfaces on this type of processor die. However, the highly developed technology needed to fabricate the processor die is not required to provide the interfaces. In light of the variability of requirements related to special interfaces, it is also more practical to provide a separate interface. Additional reasons relate to fabrication parameters and material parameters, for example, dielectric strength. To connect a processor core of the control device on a processor die to an interface control device, for example an interface chip, a bus is required that is fast, requires few lines, has few overheads, and enables different types of transmission. For example, the bus addresses register and memories individually, or enables direct memory access.
What is needed is a bus system with a bus which is the interface between a processor core with a conventional bus terminal and interface devices associated with additional system devices and peripherals.